1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for implementing control of access to a controlled device (for example, a serial interface flash memory or the like), for example, a circuit structure for switching an operation mode in accordance with type or the like of a flash memory.
2. Description of the Related Art
Ordinarily, external memories (for example, serial interface flash memories, which are non-volatile memories formed such that writing, erasure and the like of information can be implemented electronically) that can be connected to a semiconductor integrated circuit featuring serial access functions (for example, a large-scale integrated circuit, below referred to as an LSI) feature unrelated command codes for different types of memory. A type can be identified with a command for reading identification information of a flash memory (below referred to as ID information), but a command code for the ID information reading command differs for the different types of flash memories. Therefore, identification of flash memory types cannot be performed with a common command code. A technology for solving this problem has been disclosed in, for example, Japanese Patent Application Laid-Open (JP-A) No. 2004-234129.
Therein, technology of a memory identification circuit for a semiconductor integrated circuit is disclosed. When an external memory (for example, a flash read-only memory, below referred to as a flash ROM) connected to a semiconductor integrated circuit featuring memory access functions is changed, it is necessary for setting of optimal control registers for the connected flash ROM by control code transfer software and for re-writing new control codes and the like from an external communications unit to random access memory (below referred to as RAM). Therefore, operations are complicated and universal applicability is lacking.
In order to solve these problems, the technology of JP-A No. 2004-234129 employs the following structure. In this structure, terminal states are identified by a plurality of terminals provided at the semiconductor integrated circuit which can be pulled-up/pulled-down, and a bus width is determined. A product number or the like is read from the flash ROM and the flash ROM is determined. A register of a control section provided in the semiconductor integrated circuit is set and specifications and the like are determined. Specifications which are required for access to the flash ROM, processing of terminals that are required for connection, and suchlike are set at this register.
With such a structure, there is no need for a central processing unit provided in the semiconductor integrated circuit (below referred to as a CPU) to preparatorily implement settings relating to connection of the flash ROM and execution of writing commands with control code transfer software. Therefore, there is an advantage in that it is possible to implement connection without performing complex processing. However, because of structure for reading the product number and the like from the flash ROM and determining the flash ROM, circuit structure and/or functioning of the semiconductor integrated circuit is more complicated.
As a technology for solving this problem, for example, a dedicated pin is provided at the exterior of the LSI and a signal for identifying a flash memory type is sent through this dedicated pin. An example of this structure is shown in FIG. 2.
FIG. 2 is a schematic structural diagram showing an example of a conventional system LSI which is capable of accessing two types of serial interface flash memory.
This system LSI 10 is a system which is capable of accessing controlled devices 21 and 22 (for example, serial interface flash memories of two types for which command codes differ), and is provided with plural I/O cells 11-1 to 11-6, which are input/output ports (below referred to as I/O ports). Either one of the two types of flash memory 21 and 22 is connected to the IO cells 11-3 to 11-6. The flash memory 21 or 22 includes serial interface terminals SIF1 to SIF4, which are connected to the I/O cells 11-3 to 11-6. The flash memory 21 or 22 stores a program for operating the system LSI 10. Whichever of the flash memories 21 and 22 is connected to the system LSI 10, and the connecting pins at the system LSI 10 are same for either type.
The I/O cell 11-1 of the system LSI 10 is a circuit at which a negative polarity (Neg polarity) asynchronous reset signal ‘rstn’ is inputted from outside. This I/O cell 11-1 is connected to a flash memory control circuit 12, which is for controlling the flash memory 21 or 22, and a microcontroller (below referred to as an MCU) 13, at which a CPU, memory and peripheral functions are integrated for executing programs. The flash memory control circuit 12 includes functions for sending and receiving flash memory interface input signals fsif1 to fsif4 through the I/O cells 11-3 to 11-6, and sending and receiving signals to and from the MCU 13, and so forth.
The MCU 13 is connected to the flash memory control circuit 12 and is connected to a boot ROM (below referred to as BOOT_ROM) 14, a RAM 15, and the I/O cell 11-2. The BOOT_ROM 14 is a memory which retains a post-reset startup operation program, and is accessed by the MCU 13. The RAM 15 is a memory which retains a program for usual operations of the system LSI 10, and is accessed by the flash memory control circuit 12 and the MCU 13. The I/O cell 11-2 is a circuit which inputs a one-bit (below referred to as ‘bit’) identification signal ‘type’, which is for identifying the type of flash memory, from outside and supplies the identification signal type to the MCU 13.
The system LSI 10 includes circuits which are required for structuring a system LSI, such as a clock generation circuit for generating a clock signal clk and so forth. For simplicity of description, these are not illustrated.
FIG. 3 is a schematic structural diagram showing the flash memory control circuit 12 of FIG. 2. This flash memory control circuit 12 is reset by the reset signal rstn. The flash memory control circuit 12 includes a register 12a of, for example, eight bits which stores a command code for a flash memory command that is to be executed. The flash memory control circuit 12 includes functions for sending and receiving signals such as flash memory interface input/output signals fsif1 to fsif4, which are for controlling the flash memory 21 or 22, a control signal cmcu, which is for controlling the MCU 13, and a control signal cRAM, which is for controlling the RAM 15. In this structure, for example, when a command to the flash memory 21 or 22 is to be implemented, the MCU 13 determines the flash memory type from the value of the identification signal type and writes the value of a command code to the register 12a. 
Next, operations of the system LSI 10 shown in FIG. 2 and FIG. 3 will be schematically described.
In a process of identification of the flash memory 21 or 22 connected to the system LSI 10, for example, if the flash memory 21 is connected, a logical value ‘0’ is provided from outside as the identification signal ‘type’, or if the flash memory 22 is connected, a logical value ‘1’ is provided from outside as the identification signal type.
A program for usual operations of the system LSI 10 is stored at the flash memory 21 or 22. At the system LSI 10, after a reset of the flash memory control circuit 12 and the MCU 13 by the reset signal rstn, firstly, the MCU 13 executes the program in the BOOT_ROM 14 as a startup operation. In the BOOT_ROM 14, a program is stored, which is for reading out data in the flash memory 21 or 22 (which is the program for usual operations) and storing the data to the RAM 15. After the program from the flash memory 21 or 22 is stored to the RAM 15, the MCU 13 executes the program in the RAM 15.
For reading from the flash memory 21 or 22 in the startup operation, and for writing and reading operations respect to the flash memory 21 or 22 in usual operations, the MCU 13 executes commands to the flash memory 21 or 22 by controlling the flash memory control circuit 12.
Ordinarily, because command codes for the flash memories 21 and 22 differ depending on the flash memory types, the MCU 13 identifies the flash memory type from the value ‘1’ or ‘0’ of the identification signal inputted through the I/O cell 11-2, and writes a command code corresponding to this type to the register 12a in the flash memory control circuit 12. Hence, control in accordance with the flash memory type is implemented.
The flash memory control circuit 12 receives the control signal cmcu from the MCU 13 and controls the flash memory 21 or 22. In the case of reading from the flash memory 21 or 22, data read from the flash memory 21 or 22 is stored in the RAM 15. In the case of writing to the flash memory 21 or 22, data read from the RAM 15, described later, is written to the flash memory 21 or 22.
FIG. 4 is a flowchart showing operations from a reset of the system LSI 10 of FIG. 2 until the program in the flash memory has been downloaded to the RAM 15 by the startup operation program of the BOOT_ROM 14. These operations will be described below.
When a reset signal rstn asserted at the MCU 13 is released (step S1), the MCU 13 reads the boot program for startup operations stored in the BOOT_ROM 14 and starts execution of this program (step S2).
Firstly, in operations of the program that was stored in the BOOT_ROM 14, from the value of the flash memory identification signal type (i.e., for example, ‘0’), the MCU 13 determines the type of the flash memory connected to the system LSI 10 (i.e., the flash memory 21) and stores a command code of a ‘read’ command corresponding to that type into the register 12a in the flash memory control circuit 12 (step S3). Then, the MCU 13 outputs an instruction for performing the command for reading flash memory data respect to the flash memory control circuit 12 (step S4). The flash memory control circuit 12 converts the data stored in the register 12a to serial data, and sends the data to the flash memory 21 (step S5). The flash memory 21, which has received this reading command, returns serial data to the flash memory control circuit 12 (step S6). The flash memory control circuit 12 converts the received serial data to parallel data and writes the data to the RAM 15 (step S7). When the program from in the flash memory 21 is completely stored in the RAM 15 (step S8), the reading command finishes, and the MCU 13 starts usual operations in accordance with the program that has been downloaded to the RAM 15 (step S9).
Although not shown in the flowchart, when another flash memory command, such as for data-writing or the like, is to be executed to the flash memory 21 or 22, similarly to the reading command, a command code is written to the register 12a in the flash memory control circuit 12, and execution of the command to the flash memory 21 or 22 is implemented with the command code corresponding to the type.
However, in the structure of FIG. 2, it is necessary to assign a dedicated pin of the I/O cell 11-2 for input of the type identification signal type for the flash memory 21 or 22. In the structural example of FIG. 2, the identification signal type requires one pin for selection of the two types, but the number of identification signal pins will increase in accordance with the number of corresponding types.
When type identification information is stored in the startup operation for type identification of the flash memory 21 or 22, there is no need for the type identification signal type to be inputted in subsequent operations. Therefore, in the conventional structure, because the dedicated pin(s) is/are assigned to the identification signal type which is required only in startup operations, chip size is wastefully increased. Apart from flash memory, this also arises with other controlled devices to be accessed by a semiconductor integrated circuit.